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Modicon Ladder Logic Block Library User Guide 840 USE 101 00 Version 3.0 August 2001 Schneider Electric One High Street North Andover , MA 01845 Preface Thedataandillustrations found in this book are not binding. We reserve the right to modify our products in line with our policy of continuous product development. The information in this document is subject to change without notice and should not be construed as a commitment by Schneider Electric. Schneider Electri c assumes no responsibility for any errors that may appear in this document. If you have any suggestions for improvements or amendments or have found errors in this publication, please notify us by using the form on the last page of this publication. Nopartofthis document may be reproduced in any form or by any means, electronic or mechanical, including photocopying, without express written permission of the Publisher, Schneider Electric. Caution: All pertinent state, regional, and local safety regulations must be observed when installing and using this product. For reasons of safety and to assure compliance with documented system data, repairs to components should be performed only by the manufacturer . MODSOFT is a registered trademark of Schneider Electric. The following are trademarks of Schneider Electric. Modicon QuantumAutomationSeries ModbusPlus Modbus ModbusII 984 PLC Compact984PLC Modicon Micro PLC DIGITALandDECareregisteredtrademarksofDigitalEquipment Corporation. IBMandIBMATareregisteredtrademarksofInternational Business Machines Corporation. Microsoft and MSDOSare registered trademarks of Microsoft Corporation. Copyright 20 01, Schneider Electric Printed in U.S.A. 840USE10100 Preface iii Contents Chapter 1 Ladder Logic Overview ........................... 1 1.1 SegmentsandNetworksinLadderLogic ......................... 2 1.1.1 ALadderLogicNetwork ............................. 2 1.1.2 Coil Placement in a Network ......................... 3 1.1.3 Ladder Logic Segments .............................. 4 1.2 HowaPLCSolvesLadderLogic ................................. 5 1.3 Ladder Logic Elements and Instructions .......................... 7 Chapter 2 Memory Allocation in a PLC ....................... 11 2.1 UserMemory .................................................. 12 2.1.1 User Logic .......................................... 12 2.1.2 User Memory ....................................... 12 2.1.3 SystemOverhead ................................... 13 2.1.4 MemoryBackup .................................... 13 2.2 State RAMValues .............................................. 14 2.2.1 AReferencing System for Inputs and Outputs ......... 14 2.2.2 Storing Discrete and Register Data in State RAM ...... 15 2.3 State RAMStructure ........................................... 16 2.3.1 MinimumRequiredStateRAMValues ................ 17 2.3.2 History and Disable Bits for Discrete References ....... 17 2.4 TheConfiguration Table ........................................ 18 2.4.1 Assigning a Battery Coil ............................. 18 2.4.2 Assigning a Timer Register .......................... 18 2.4.3 TheTimeofDayClock ............................... 19 2.4.4 Configuration Overview ............................. 20 2.5 TheI/OMapTable.............................................. 22 2.5.1 Determining the Size of the I/O Map Table ............. 22 2.5.2 Writing Data to the I/O Map Table .................... 22 840 USE 101 00 v Contents Chapter 3 Ladder Logic Opcodes ........................... 23 3.1 Translating Ladder Logic Elements in System Memory ............ 24 3.1.1 Translating Logic Elements and Non-DX Functions .... 24 3.2 Translating DX Instructions in the System Memory Database ...... 26 3.2.1 HowthexandzBitsAreUsedin16-bitNodes ......... 26 3.2.2 HowthexandzBitsAreUsedin24-bitNodes ......... 27 3.2.3 Opcodes for Standard DX Instructions ................ 28 3.2.4 HowtheyBitsareUtilizedforDXFunctions .......... 28 3.3 OpcodeDefaults for Loadables ................................... 29 3.3.1 HowtoHandleOpcodeConflicts ...................... 29 Chapter 4 Ladder Logic Elements ........................... 31 4.1 Contacts ....................................................... 32 4.1.1 Normally Open Contacts ............................. 32 4.1.2 Normally Closed Contacts ............................ 33 4.1.3 Positive Transitional Contacts ........................ 33 4.1.4 Negative Transitional Contacts ....................... 34 4.2 Coils .......................................................... 36 4.2.1 NormalCoils ....................................... 36 4.2.2 Latched or Memory-retentive Coils ................... 36 4.2.3 ASimpleContact-Coil logic Example .................. 37 4.2.4 Coil Usage in a Logic Network ........................ 37 4.2.5 General Coil Usage Guidelines ....................... 38 4.3 Shorts ......................................................... 39 4.3.1 Horizontal Shorts ................................... 39 4.3.2 Vertical Shorts ...................................... 39 4.4 Using Logic Elements to Create Control Circuits .................. 40 4.4.1 ALogical ANDCircuit ............................... 40 4.4.2 ALogical OR Circuit ................................ 40 4.4.3 ALogical XORCircuit ............................... 41 4.4.4 Building a Seal Circuit .............................. 41 4.5 Storing Contacts and Coils in Registers ........................... 43 4.6 NOBT ......................................................... 45 4.7 NCBT ......................................................... 47 4.8 NBIT.......................................................... 49 4.9 SBIT .......................................................... 51 4.10 RBIT .......................................................... 53 vi Contents 840 USE 101 00
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